module ff_cell(clk, rst, d_in, d_out);
input      clk;
input      rst;
input      d_in;
output reg d_out;

always @(posedge clk or posedge rst) begin
   if (rst)
      d_out <= 1'b0;
   else
      d_out <= d_in;
end

endmodule


module shift_reg_struct(clk, rst, ser_in, ser_out);
parameter LENGTH = 4;
input  clk;
input  rst;
input  ser_in;
output ser_out;

wire [(LENGTH-1):0] shift_reg;

generate
genvar i; 
   for (i=0 ; i<LENGTH; i=i+1) begin: ff_gen
      if (i==0)
         ff_cell ff_inst(.clk(clk), .rst(rst), .d_in(ser_in), .d_out(shift_reg[i]));
      else
         ff_cell ff_inst(.clk(clk), .rst(rst), .d_in(shift_reg[i-1]), .d_out(shift_reg[i]));
   end
endgenerate

assign ser_out = shift_reg[LENGTH-1];

endmodule
